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n mu @ mcs@ 51 8-bit control-oriented microcontrollers commercial/express 8031 ah18051ah18051ahp 8032n+18052n-i 8751 w8751h-8 8751bw8752bi-i n high performance hmos process n n internal timers/event counters n n 2-level interrupt priority structure n n 32 1/0 lines (four 8-bit ports) n 64k external program memory space n n security feature protects eprom parts n against software piracy n boolean processor bit-addressable ram programmable full duplex serial channel 111 instructions (64 single-cycle) 64k external data memory space extended temperature range (?40?c to +85?c) the mcs@ 51 controllers are optimized for control applications. byte-processing and numerical operations on small data structures are facilitated by a variety of fast addressing modes for accessing the internal ram. the instruction set provides a convenient menu of 8-bit arithmetic instructions, including multiply and divide instruc- tions. extensive on-chip support is provided for one-bit variables as a separate data type, allowing direct bit manipulation and testing in control and logic systems that require boolean processing. the 8751 h is an eprom version of the 8051 ah. it has 4 kbytes of electrically programmable rom which can be erased with ultraviolet light. his fully compatible with the 8051ah but incorporates one additional feature: a program memory security bit that can be used to protect the eprom against unauthorized readout. the 8751 h-8 is identical to the 8751 h but only operates up to 8 mhz. the 8051ahp is identical to the 8051ah with the exception of the protection feature. to incorporate this protection feature, program verification has been disabled and external memory accesses have been limited to 4k. the 8052ah is an enhanced version of the 8051 ah. it is backwards compatible with the 8051 ah and is fabricated with hmos ii technology. the 8052ah enhancements are listed in the table below. also refer to this table for the rom, romless and-eprom versions of each product. device intsrnal memory timera/ event counters interrupts program data 8031ah none 128 x 8 ram 2 x 18-bit 5 8051ah 4k x 8 rom 128 x 8 ram 2 x 16-bit 5 6051ahp 4k x 6 rom 128 x 8 ram 2 x 16-bit 5 8751 h 4k x 8 eprom 128 x 8 ram 2 x 16-bit 5 8751 h-8 4k x 8 eprom 128 x 6 ram 2 x 16-bit 5 6751 bh 4k x 8 eprom 128 x 8 ram 2 x 16-bit 5 8032ah none 256 x 6 ram 3 x 16-bit 6 6052ah 8k x 8 rom 256 x 8 ram 3 x 16-bit 6 8752bh 8k x 8 eprom 256 x 8 ram 3 x 16-bit 6 i intel corporation assumes no responsibility for the use of any circuit~ other than circuitry embodied in an intel product. no other circuit patent licenses are implied. information contained herein supersedes previously published specifications on theaa davices from intel. o intel corporation, 1994 october 1994 order numben 272318-002
mcs? 51 controller mo-m 7 p2.&p2 7 - i i i fl 13 i i ii ,, , jk2u acc b stack pointer ~m ?f2#fi+-on,tmod,tj +1 l? l-j i <>1 i 1 ml i . . . ,, , i 7?7 1 . . . . . 9 psen ale ?% ? tyg g~ e rst-+ ?* ii i 1==4 119 p0nt3 h-+ t latch n i- ,,(-1 - - % = 2 w pi o*1 7 5 pm lhvi!rs ??????????? p] o-p3 7 7 w 3 i ????? ?.. j x = 272318-1 figure 1. mcsi@ 51 controller block diagram process information the 8031 ah/8051ah and 8032ah/8052ah devic- es are manufactured on p414.1, an hmos ii pro- cess. the 8751 h/8751 h-8 devices are manufac- tured on p421 .x, an hmos-e process. the 8751 bh and 8752bh devices are manufactured on p422. additional process and reliability information is avail- able in intel?s components quality and reliability handbook, order no, 210997.
mcs@ 51 controller packages part prefix package type ?ja ojc 8051ah p 40-pin plastic dip 45chv 16?c/w 8031 ah d 40-pin cerdip 4!5?ciw 15?caiv 8052ah n 44-pin plcc 46c/w 18cfw 8032ah 6752bh* 8751 h d 40-pin cerdip 45?ciw 45?ciw 8751 h-8 8051ahp p 40-pin plastic dip 45?ciw 16cf w d 40-pin cerdip 45c/w 15?cf w 8751 bh p 40-pin plastic dip 36?ciw 12cf w n 44-pin plcc 47?c1w 16?cf w note: *8752bh is 36?/10? for d, and 38?/22? for n. all thermal impedance data is approximate for static air conditions at iw of power dissipation. values will change depending on operating conditions and application. see the intel pac/raging handbook (order number 240800) for a description of intel?s thermal impedance test methodology. ~?52?80320nl? ~ l { t2 t2ex i?__?ll pi.? 1 40 vcc p1.1 2 39 p?,? p1.2 3 38 po.1 p1.3 4 37 po.2 p1.4 5 36 po.3 p1.5 6 35 po.4 p1,6 7 34 po.5 p1.7 6 33 p06 ?1 rst 9 ru2 p3.o 10 txd p3.1 11 into p3.2 12 int1 p3,3 13 to p3 4 14 11 p3.5 15 ~ p3.6 16 t% p3.7 17 xtal2 16 xtal1 19 ?ss +!-- 29 26 27 26 25 24 23 22 21 ado ad1 a02 a03 ad4 ad5 ad? 3 po.7 a07 3 eijvpp? z aleiprog? 3%ffi 3 p2.7 a15 2 p2.6a14 3 p2.5 a13 i p2.4 a12 1 p2.3 al 1 > p2.2 alo 3 p2 1 a9 x p20 a8 pi.6 ::8:; p*,7 .:,. : rst io; (rxo) p3.o :ji: neaslvsd** .1:; ftxd) p3.1 :ji; (into) p3.2 :!;; (int1) p3.3 :j:; fto) p3.4 :>!: 8x5x 272318-2 dip plcc l eprom only ?*do not connect reserved pins. figure 2. mcs@ 51 controller connections 3
mcs? 51 controller pin descriptions vcc: supply voltage. vss: circuit ground. port o: port o is an 8-bit open drain bidirectional 1/0 port. as an output port each pin can sink 8 ls ttl inputs. port o pins that have 1?s written to them float, and in that state can be used as high-impedance inputs. port o is also the multiplexed low-order address and data bus during accesses to external program and data memory. in this application it uses strong inter- nal pullups when emitting 1?s and can source and sink 8 ls ttl inputs. port o also receives the code bytes during program- ming of the eprom parts, and outputs the code bytes during program verification of the rom and eprom parts. external pullups are required during program verification. port 1: port 1 is an 8-bit bidirectional 1/0 port with internal pullups, the port 1 output buffers can sink/ source 4 ls ttl inputs. port 1 pins that have 1?s written to them are pulled high by the internal pull- ups, and in that state can be used as inputs. as inputs, port 1 pins that are externally pulled low will source current (iil on the data sheet) because of the internal pullups. port 1 also receives the low-order address bytes during programming of the eprom parts and during program verification of the rom and eprom parts. in the 8032 ah, 8052ah and 8752bh, port 1 pins p1.o and p1.1 also serve the t2 and t2ex func- tions, respectively. w port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (movx @dptr). in this application it uses strong internal pullups when emitting 1?s. dur- ing accesses to external data memory that use 8-bit addresses (movx @ri), port 2 emits the contents of the p2 special function register. port 2 also receives the high-order address bits dur- ing programming of the eprom parts and during program verification of the rom and eprom parts. the protection feature of the 8051 ahp causes bits p2.4 through p2.7 to be forced to o, effectively limit- ing external data and code space to 4k each during external accesses. port 3: port 3 is an 8-bit bidirectional l/o port with internal pullups. the port 3 output buffers can sink/ source 4 ls ttl inputs. port 3 pins that have 1?s written to them are pulled high by the internal pull- ups, and in that state can be used as inputs. as inputs, port 3 pins that are externally pulled low will source current (iil on the data sheet) because of the pullups. port 3 also serves the functions of various special features of the mcs 51 family, as listed below: port pin p3,0 p3.1 p3.2 p3,3 p3.4 p3.5 p3.6 p3.7 alternative function rxd (serial input port) txd (serial output port) into (external interrupt o) int1 (external interrupt 1) to (timer o external input) t1 (timer 1 external input) wr (external data memory write strobe) ~ (external data memory read strobe) i port pin i alternative function i p1 .0 t2 (timer/counter 2 external input) p1 .1 t2ex (timer/counter 2 capture/reload trigger) port 2: port 2 is an 8-bit bidirectional l/o port with internal pullups. the port 2 output buffers can sink/ source 4 ls ttl inputs. porl 2 pins that have 1?s written to them are pulled high by the internal pull- ups, and in that state can be used as inputs. as inputs, port 2 pins that are externally pulled low will source current (iil on the data sheet) because of the internal pullups. rst: reset input. a high on this pin for two machine cycles while the oscillator is running resets the de- vice, ale/prog: address latch enable output pulse for latching the low byte of the address during accesses to external memory. this pin is also the program pulse input (prog) during programming of the eprom parts. in normal operation ale is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. note, how- ever, that one ale pulse is skipped during each ac- cess to external data memory.
mcs? 51 controller w psen: program store enable is the read strobe to external program memory. when the device is executing code from external program memory, psen is activated twice each ma- chine cycle, except that two psen activations are skipped during each access to external data memo- ry ~/vpp: external access enable ~ must be strapped to vss in order to enable any mcs 51 de- vice to fetch code from external program memory locations starting at ooooh up to ffffh. ~ must be strapped to vcc for internal program execution. note, however, that if the security bit in the eprom devices is programmed, the device will not fetch code from any location in external program memory. this pin also receives the programming supply volt- age (vpp) during programming of the eprom parts. c2 i el xtal2 n xtal1 cl vss = 272318-3 cl, c2 = 30 pf +10 pf for crystals for ceramic resonators contact resonator manufacturer. figure 3. oscillator connections xtal1: input to the inverting oscillator amplifier. xtal2: output from the inverting oscillator amplifi- er, oscillator characteristics xtal1 and xtal2 are the input and output, respec- tively, of an inverting amplifier which can be config- ured for use as an on-chip oscillator, as shown in figure 3. either a quartz crystal or ceramic resonator may be used. more detailed information concerning the use of the on-chip oscillator is available in appli- cation note ap-1 55; ?oscillators iers,? order no, 230659. i for microcontrol- to drive the device from an external clock source, xtal1 should be grounded, while xtal2 is driven, as shown in figure 4. there are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum high and low times specified on the data sheet must be observed. external oscillator signal xtal2 xtal1 vss 272318-4 figure 4. external drive configuration express version the intel express system offers enhancements to the operational specifications of the mcs 51 family of microcontrollers. these express products are designed to meet the needs of those applications whose operating requirements exceed commercial standards. the express program includes the commercial standard temperature range with burn-in, and an ex- tended temperature range with or without burn-in. with the commercial standard temperature range, operational characteristics are guaranteed over the temperature range of o?c to + 70?c. with the ex- tended temperature range option, operational char- acteristics are guaranteed over a range of ?40?c to + 85?c. the optional burn-in is dynamic, for a minimum time of 160 hours at 125c with vcc = 5.5v * 0.25v, following guidelines in mil-std-883, method 1015. package types and express versions are identified by a one- or two-letter prefix to the part number. the prefixes are listed in table 1. for the extended temperature range option, this data sheet specifies the parameters which deviate from their commercial temperature range limits. 5
mcs@ 51 controller table 1. express prefix identification prefix package type temperature range burn-in p plastic commercial no d cerdip commercial no n plcc commercial no td cerdip extended no tp plastic extended no tn plcc extended no ld cerdip extended yes lp plastic extended yes note: contact distributor or local sales office to match express prefix with proper device. design considerations if an 8751 bh or 8752bh is replacing an 8751 h in a future design, the user should carefully com- pare both data sheets for dc or ac characteris- tic differences. note that the vih and iih specifi- cations for the ~ pin differ significantly between the devices. exposure to light when the eprom device is in operation may cause logic errors. for this reason, it is suggested that an opaque label be placed over the window when the die is exposed to am- bient light. l the 8051ahp cannot access external program or data memory above 4k. this means that the following instructions that use the data pointer only read/write data at address locations below offfh: movx a,@dptr movx (6jdptr, a when the data pointer contains an address above the 4k limit, those locations will not be ac- cessed. to access data memory above 4k, the movx @ri,a or movx a,@ri instructions must be used. 6
mcs? 51 controller absolute maximum ratings* ambient temperature under bias ?40?c to + 85c storage temperature . ?65c to + 150c voltage on ea/vpp pin to vss 8751 h . . . . . . . . . . . . . . . . . ?0.5v to + 21.5v 8751 bh/6752bh ?0.5v to + 13.ov voltage on any other pinto vss . ?0.5v to + 7v power dissipation. . . ... 1.5w operating conditions notice: this is a production data sheet. it is valid for the devices indicated in the revision history. the specifications are subject to change without notice. *warning: stressing the device beyond the ?absolute maximum ratings? may cause permanent damage. these are stress ratings orr~. operation beyond the ?operating conditions? is not recommended and ex- tended exposure beyond the ?operating conditions? may affect device reliabili~. symbol description min msx units ta ambient temperature under bias commercial o +70 ?c express ?40 +65 ?c vcc supply voltage 4.5 5.5 v fosc oscillator frequency 3.5 12 mhz dc characteristics (over operating conditions) all parameter values apply to all devices unless otherwise indicated symbol parameter min max units test conditions vil input low voltage (except ~ pin of ?0.5 0.8 v 6751h and 8751h-8) vil1 input low voltage to ~ pin of o 0.7 v 6751h and 8751 h-8 vih input high voltage (except xtal2, rst) 2.0 vcc + 0.5 v vih1 input high voltage to xtal2, rst 2.5 vcc + 0.5 v xtal1 = vss vih2 input high voltage to ~ pin 4.5 5.5v of 6751 bh and 8752bh vol output low voltage (ports 1,2, 3)* 0.45 v lol = 1.6 ma voll output low voltage (port o, ale, psen)* 8751 h, 8751 h-8 0.60 v iol = 3.2 ma 0.45 v !ol = 2.4 ma all others 0.45 v iol = 3.2 ma voh output high voltage (ports 1,2,3, ale, psen) 2.4 v ioh = ?80 pa voh1 output high voltage (port o in 2.4 v ioh = ?400 pa external bus mode) iil logical o input current (ports 1,2,3, and rst) ?500 pa vin = 0.45v iili logical o input current (~) 8751h and 8751 h-8 ?15 ma vin = 0.45v 8751bh ?lo ma vin = vss 8752bh ?lo ma vin = vss 0.5 ma 7
mcs? 51 controller dc characteristics (over operating conditions) all oarameter values armlv to all devices unless otherwise indicated (continued) ~?.-...?.?. _r r., . -. symbol parameter min max units teat conditions 11l2 logical o input current (xtal2) ?3.2 ma vin = 0.45v ili input leakage current (porf o) 8751 h and 8751 h-8 * 1 or) pa 0.45< vin < vcc all others t 10 pa 0.45< vin < vcc iih logical 1 input current (~) 8751h and 8751 h-8 500 pa vin = 2.4v 8751 bh/8752bh 1 ma 4.5v < vin < 5.5v iih1 input current to rst to activate reset 500 pa vin < (vcc ? 1.5v) icc power supply current: 8031 ah/8051 ah/8051ahp 125 ma all outputs 8032ah/8052ah/8751 bh/8752bh 175 ma disconnected; 8751 h/8751 h-8 250 ma m = vcc clo pin capacitance 10 pf test freq = 1 mhz notes: 1. capacitive loading on ports o and 2 may csuse spurious noise pulses to be superimposed on the vols of ale/prog and ports 1 and 3. the noise is due to external bus capacitance discharging into the port o and port 2 pins when these pins make 1-to-o transitions during bus operations. in the worst cases (capacitive loading > 100 pf), the noise pulse on the ale/prog pin may exceed 0.8v. in such cases it maybe desirable to qualify ale with a schmitt trigger, or use an address latch with a schmi~ trigger strobe input. 2, ale/prog refers to a pin on the 8751bh. ale refers to a timing signal that is output on the ale/prog pin. 3. under steady state (non-transient) conditions, lol must be externally limited as follows: maximum lol per port pin: 10 ma maximum lol per 8-bit pori - port o: 26 ma ports 1, 2, and 3: 15 ma maximum total tol for all output pins: 71 ma if lol exceeds the test condition, vol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 8
mcs@ 51 controller explanation of the ac symbols each timing symbol has 5 characters. the first char- acter is always a ?t? (stands for time). the other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. the following is a list of all the characters and what they stand for. a: address c: clock d: input data h: logic level high 1: instruction (program memory contents) l: ~level low, or ale p: psen q: output data r: ~ signal t: time v: valid w: wr signal x: no longer a valid logic level z: float for example, tavll = time from address valid to ale low. tllpl = time from ale low to psen low. ac characteristics (under operating conditions; load capacitance for port o, ale/prog, and psen = 100 pf; load capacitance for all other outputs = 80 pf) external program memory characteristics symbol parameter 12 mhz oscillator variable oscillator units min max min max 1 /tclcl oscillator frequency 3.5 12.0 mhz tlhll ale pulse width 127 2tclcl?40 ns tavll address valid to ale low 43 tclcl?40 ns tllax address hold after ale low 48 tclcl?35 ns tlliv ale low to valid instr in 8751 h 183 4tclcl? 150 ns all others 233 4tclcl? 100 ns tllpl ale low to psen low 58 tclcl?25 ns tplph psen pulse width 8751 h 190 3tclcl?60 ns all others 215 3tclcl?35 ns tpliv psen low to valid instr in 8751h 100 3tclcl? 150 ns all others 125 3tclcl? 125 ns tpxix input instr hold after psen o 0 ns tpxiz input instr float after psen 63 tclcl?20 ns tpxav psen to address valid 75 tclcl?8 ns taviv address to valid instr in 8751 h 287 5tclcl?1 50 ns all others 302 5tclcl?1 15 ns tplaz psen low to address float 20 20 ns trlrh ~ pulse width 400 6tclcl? 100 ns twlwh wr pulse width 400 6tclcl? 100 ns trldv ~ low to valid data in 252 5tclcl? 165 ns trhdx data hold after ~ o 0 ns trhdz data float after ~ 97 2tclcl?70 ns tlldv ale low to valid data in 517 8tclcl?1 50 ns -.. . . . . . , , . ,?, . , -?.? ,.? .,. - nl-n, n, .ec -- i avuv i aaaress 10 valla ua[a m i i dud i i y i ~lul? 103 i rm 9
mcs@ 51 controller external program memory characteristics (continued) symbol tllwl tavwl tqvwx tqvwh twhqx trlaz twhlh ?arame?er i---%# ale low to rd or wr low 200 address to ~ or wr low 203 data valid to wr transition 8751 h i 13 all others 23 data valid to wr high 433 data hold after wr 33 rd low to address float rd or wr high to ale high 8751h 33 all others 43 cillator variable oscillator units max min max 300 3tclcl?50 3tclcl+ 50 ns 4tclcl? 130 ns tclcl?70 ns tclcl?60 ns 7tclcl? 150 ns tclcl?50 ns 20 i i 20 i ns i 133 tclcl?50 tclcl+ 50 ns 123 tclcl?40 tclcl+40 ns note: ?the 8751 h-8 is identical to the 8751h but only o~erates uti to 8 mhz. when calculating the ac characteristics for the 8751 h-8, use the 8751 h formula for variable oscillators. 10
mcs@ 51 controller external program memory read cycle w--- tlhll _ ale \ , / \ tllpl - ~ tplph -tavll+ + tlliv psen / tllax port o 1 port 2 x ao -a15 x a8 -a15 272318-5 external data memory read cycle ale y \ / +tlhll+ twhlh psen ?llov ~ ? tllwl trlrh ?? m + tavll + b i ? _tllax ?trldv4 trhox+ porto ao-a7 from ri or opl oata in . . tavov b port 2 x r p2.o-p2.7 or a8-a15 from dph x a8-a15 from pch 272318-6 external data memory write cycle ale \ , \ / tlhll? twhlh m / ?tllwl~twlwh * wt 1 tavll k 1 ? +tllax 7t=- tqvwx : r twhqx tqvwh ii i 1 porto ao-a7 from rior opl m oata out xx ao-a7 from fcl i port2 x p2.o-p2.7 or a8-a15 from oph x a8-a15 from pch 272318-7 11
m=? 51 controller serial port timing?shift test conditions: over oderatina conditions: load capacitance = 80 rjf symbol txlxl tqvxh txhqx txhdx txhdv parameter 12 mhz oscillator variable oscillator unite min max min max serial port clock cycle time 1.0 12tclcl ps output data setup to clock rising 700 1otclcl? 133 ns edge output data hold after clock 50 2tclcl?1 17 ns rising edge input data hold after clock rising o 0 ns edge clock rising edge to input data 700 10tclcl? 133 ns valid ;hi17 register mode timing waveforms instruction i o i 1 i 2 i 3 i 4 i 5 i 6 i 7 i 8 i ale n n n n n n n n n n n n n n n n n n i i-txlxl-7 clock wi-txhqx i output oata o 1)( 1 2 x 3 x 4 x 5 x 6 x 7 / , + set ti input data ~ 4 set ri 272318-8 12
mcs@ 51 controller external clock drive symbol parameter min max units 1 1 /tclcl oscillator frequency (except 8751 h-8) 3.5 12 mhz 8751 h-8 3.5 8 mhz tchcx high time 20 ns tclcx low time 20 ns i tclch i rise time i i 20 i ns i tchcl fall time 20 ns external clock drive waveform ? tchcx ? tclch _ ? ? ~ tclicl 2.5 t a t 2.5 a -? tclcx ? + tclcl w 272318-9 ac testing input, output waveform 2.4 2.0 2.0 >< test points 0.s 0.8 0.45 272318-10 ac testing: inputs are driven at 2.4v for a logic ?1? and 0.45v for a logic ?o?. timing measurements ara made at 2.ov for a logic ?1? and 0.8v for a logic ?o?.
mcs@ 51 controller eprom characteristics table 3. eprom programming modea mode rst psen ale m p2.7 p2.6 p2.5 p2.4 program 1 0 o* vpp 1 0 x x verify 1 0 1 1 0 0 x x security set 1 0 o* vpp 1 1 x x note: ?1? = logic high for that pin ?o? = logic low for that pin ?x? = ?don?t care? programming the 8751h to be programmed, the part must be running with a 4 to 6 mhz oscillator. (the reason the oscillator needs to be running is that the internal bus is being used to transfer address and program data to appro- priate internal registers.) the address of an eprom location to be programmed is applied to port 1 and pins p2.o-p2.3 of port 2, while the code byte to be programmed into that location is applied to port o. the other porl 2 pins, and rst, psen, and ~/vpp should be held at the ?program? levels indicated in table 3. ale/prog is pulsed low for 50 ms to pro- gram the code byte into the addressed eprom lo- cation. the setup is shown in figure 5. normally ~~is held at a logic highflntil just before ale/prog is to be pulsed. then ea/vpp is raised to +21 v, ale/prog is pulsed, and then ~/vpp is returned to a logic high. waveforms and detailed timing specifications are shown in later sec- tions of this data sheet. +5v a vcc aoor a&b? p? ?ffh w pgm data p2.0? u?all p2.3 8751h ?=??-?tcarej=e ?lel=$=- u vlli p2.7 xtau 5 f&vpp 4-sun* n xtal1 rst vih1 vss psen . . 27231 a-1 i figure 5. programming configuration ?vpp? = +21v *0.5v *ale is pulsed low for 50 ms note that the ~/vpp pin must not be allowed to go above the maximum specified vpp level of 21 .5v for any amount of time. even a narrow glitch above that voltage ievei can cause permanent damage to the device. the vpp source should be well regulated and free of glitches. program verification if the security bit has not been programmed, the on- chip program memory can be read out for verifica- tion purposes, if desired, either during or after the programming operation. the address of the program memory location to be read is appiied to port 1 and pins p2.o-p2.3. the other pins should be held at the ?verify? ieveis indicated in tabie 3. the contents of the addressed location will come out on port o. ex- ternal pullups are required on port o for this opera- tion. the setup, which is shown in figure 6, is the same as for programming the eprom except that pin p2.7 is held at a logic low, or may be used as an active- iow read strobe +5v ? vcc mu w + data ?ffh (use 10k pullups] w51h x ~ . ,, w,, care,. - ~~b x-9 p2.5 ale vil d p2.s vih enas4e . p2 7 g j- xtau 4-6 mhz m rst h vih1 xtal1 vss psen . 27231s-12 figure 6. program verification 14
mcs@ 51 controller eprom security the security feature consists of a ?locking? bit which when programmed denies electrical access by any external means to the on-chip program memory. the bit is programmed as shown in figure 7. the setup and procedure are the same as for normal eprom programming, except that p2.6 is held at a logic high, porl o, port 1 and pins p2.o?p2.3 may be in any state. the other pins should be held at the ?security? levels indicated in table 3. once the security bit has been programmed, it can be cleared only by full erasure of the program mem- ory. while it is programmed, the internal program memory can not be read out, the device can not be further programmed, and it can not execute out of external program memory. erasing the eprom, thus clearing the security bit, restores the device?s full functionality. it can then be reprogrammed. + 5v x = ogn?t care? o f vcc {: ?- pi m x p2.0- x p2.3 8751h p2.4 ale ale/proo p2.5 50 ma pulse to gnd p2.6 vim p2,7 fi + eaypp xtau m rst ? wh1 xtal1 vss psen 7 * * 272318-13 erasure characteristics erasure of the eprom begins to occur when the device is exposed to light with wavelengths shorter than approximately 4,000 angstroms. since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources over an ex- tended time (about 1 week in sunlight, or 3 years in room-level fluorescent lighting) could cause inadver- tent erasure. if an application subjects the device to this type of exposure, it is suggested that an opaque label be placed over the window. figure 7. programming the security bit the recommended erasure procedure is exposure to ultraviolet light (at 2537 angstroms) to an integrat- ed dose of at least 15 w-sec/cm2. exposing the eprom to an ultraviolet lamp of 12,000 pw/cm2 rating for 20 to 30 minutes, at a distance of about 1 inch, should be sufficient. erasure leaves the array in an all 1?s state. eprom programming and verification characteristics ta = 21c to 27?c; vcc = 5v + 10%; vss = ov symbol parameter min max unita vpp programming supply voltage 20.5 21.5 v ipp programming supply current 30 ma 1 /tclcl oscillator frequency 4 6 mhz tavgl address setup to prog low 46tclcl tghax address hold after prog 48tclcl tdvgl data setup to prog low 48tclcl tghdx data hold after~ 48tclcl tehsh p2.7 (enable) high to vpp 48tclcl tshgl vpp setup to prog low 10 ps tghsl vpp hold after prog 10 ps tglgh prog width 45 55 ms tavqv address to data valid 48tclcl telqv enable low to data valid 48tclcl tehqz data float after enable o 48tclcl 15
mcs? 51 controller gi-? ?nl r??? ?mrnmrlmn. w i-8. ? ,lrl.. .?4-s . m?.. ..-. b. ?..8.,? programming verification p1.o-pi.7 p3,0-p3,3 ( address $ j ? port o { , data in tovgl ? ? ?tghox tavgl ? tghax kle/prog \ ~ ? tshgl ? ? ? tghsl tglgh 21v * .5v r \ m high fi.vpp ttl high ttl high tshsn ? telov p3.7 (enable) 1 ? \ 272318-14 for programming conditions see figure 5. for verification conditions see figure 6. 16
inla mcs? 51 controller programming the 8751 bh/8752bh to be programmed, the 875xbh must be running with a 4 to 6 mhz oscillator. (the reason the oscilla- tor needs to be running is that the internal bus is being used to transfer address and program data to appropriate internal registers.) the address of an eprom location to be programmed is applied to porl 1 and pins p2.o - p2.4 of port 2, while the code byte to be programmed into that location is applied to port o. the other port 2 and 3 pins, and rst, psen, and ~/vpp should be held at the ?program? levels indicated in table 1. ale/prog is pulsed low to croaram the code bvte into the addressed normally ~&is held at a logic high until just before ale/prog is to be pulsed. then ~/vpp is raised to vpp, ale/prog is pulsed low, and then ~/vpp is returned to a valid high voltage. the volt- age on the ~/vpp pin must be at the valid ea/vpp high level before a verify is attempted. waveforms and detailed timing specifications are shown in later sections of this data sheet. note that the ~/vpp pin must not be allowed to go above the maximum specified vpp level for any amount of time. even a narrow glitch above that volt- age level can cause permanent damage to the de- vice. the vpp source should be well regulated and eprofl location. the setu?p is shown in figure 8. free of glitches. +5v vcc po 1 ~ rst e/vpp ~ +12.75v ale/prog ~25 100 p, pulses to gnd 1 ~ p3.6 875x,, ~ ~? 1 ~ p3.7 p2.7 ~1 lj- xtal 2 p2.6 ~o 4-6 mhz q t= ; xtal 1 p2. o -p2,4 ?ks = 272318-15 ?. ? figure 8. programming the eprom table 4. eprom programming modea for 875xbh mode rst ale/ psen ? ml prog vpp p2.7 p2.6 p3.6 p3.7 program code data 1 0 o* vpp 1 0 1 1 verify code data 1 0 1 1 0 0 1 1 program encryption tabie 1 0 o* vpp 1 0 0 1 use addresses o-1 fh program lock ~= 1 1 0 o* vpp 1 1 1 1 bits (lbx) x=2 1 0 o* vpp 1 1 0 0 read signature 1 0 1 1 0 0 0 0 notes: ?1? = valid high for that pin ?o? = valid low for that pin ?vpp? = + 12.75v + 0.25v *ale/prog is pulsed low for 100 us for programming. (quick-pulse programming) 17
mcs@ 51 controller quick-pulse programming algorithm the 875xbh can be programmed using the quick- pulse programming algorithm for microcontrollers. the features of the new programming method are a lower vpp (12.75 volts as compared to 21 volts) and a shorter programming pulse. for example, it is pos- sible to program the entire 8 kbytes of 875xbh eprom memory in less than 25 seconds with this algorithm! to program the part using the new~rithm, vpp must be 12,75 f 0.25 volts. ale/prog is pulsed low for 100 pseconds, 25 times as shown in figure 9, then, the byte just programmed may be verified. after programming, the entire array should be verified. the program lock features are pro- grammed using the same method, but with the setup as shown in table 4. the only difference in program- ming lock features is that the lock features cannot be directly verified. instead, verification of program- ming is by observing that their features are enabled. program verification if the lock bits have not been programmed, the on- chip program memory can be read out for verifica- tion purposes, if desired, either during or after the programming operation. the address of the program memory location to be read is applied to port 1 and pins p2.o - p2.4. the other pins should be held at the ?verify? levels indicated in table 1. the con- tents of the addressed location will come out on port o. external pullups are required on port o for this operation. (if the encryption array in the eprom has been programmed, the data present at port o will be code data xnor encryption data. the user must know the encryption array contents to manual- ly ?unencrypt? the data during verify.) the setup, which is shown in figure 10, is the same as for programming the eprom except that pin p2.7 is held at a logic low, or may be used as an active low read strob~. , ~25p?lses ~ alem n-------- i ? 10 p,min 100jm *lops ale/prog : 0 1 272318-16 figure 9. prog waveforma +~v ?r h 10kjl ao-a7 p! rst p3.6 1 p3.7 l xtal 2 4-6 mhz q xtal 1 vss = vcc -f? x8 po pgm data rmpp ale/prw 1 b75xbh = 0 p2.7 0 (i-mm p2.6 0 p2. o -p2.4 f a8-a12 272318-17 figure 10. verifying the eprom 18
program memory lock the two-level program lock system consists of 2 lock bits and a 32-byte encryption array which are used to protect the program memory against soft- ware piracy. encryption array within the eprom array are 32 bytes of encryption array that are initially unprogrammed (all 1s). every time that a byte is addressed during a verify, 5 ad- dress lines are used to select a byte of the encryp- tion array. this byte is then exclusive-nored (xnor) with the code byte, creating an encrypted verify byte. the algorithm, with the array in the un- programmed state (all 1s), will return the code in its original, unmodified form. it is recommended that whenever the encryption ar- ray is used, at least one of the lock bits be pro- grammed as well. lock bits also included in the eprom program lock scheme are two lock bits which function as shown in table 5. erasing the eprom also erases the encryption ar- ray and the lock bits, returning the part to full un- locked functionality. mcs@ 51 controller table 5. lock bits and their features logic enabled lb1 u = minimum program lock features enabled. (code verify wiii still be p u movc instructions executed from external program memory are disabled from fetching code bytes from internal memory, ea is sampled and latched on reset, and further programming of the eprom is disabled p i p same as above, but verify is also disabled u i p ireservedfor future definition i = programmed = unprogrammed reading the signature bytes the signature bytes are read by the same procedure as a normal verification of locations 030h and 031 h, except that p3.6 and p3.7 need to be pulled to a logic low. the values returned are: (030h) = 89h indicates manufactured by intel (031h) = 51h indicates 8751bh 52h indicates 8752bh to ensure proper functionality of the chip, the inter- nally latched value of the ~ pin must agree with its external state. 19
mcs? 51 controller erasure characteristics erasure of the eprom begins to occur when the 8752bh is exposed to light with wavelengths shorter than approximately 4,000 angstroms. since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources over an ex- tended time (about 1 week in sunlight, or 3 years in room-level fluorescent lighting) could cause inadver- tent erasure. if an application subjects the device to this type of exposure, it is suggested that an opaque label be placed over the window. the recommended erasure procedure is exposure to ultraviolet light (at 2537 angstroms) to an integrat- ed dose of at lease 15 w-see/cm. exposing the eprom to an ultraviolet lamp of 12,000 pw/cm rat- ing for 30 minutes, at a distance of about 1 inch, should be sufficient. erasure leaves the array in an all is state. eprom programming and verification characteristics (t,4 = 21c to 27?c, vcc = 5.ov + 10%, vss = ov) symbol parameter min max units vpp programming supply voltage 12.5 13.0 v ipp programming supply current 50 ma 1 /tclcl oscillator frequency 4 8 mhz tavgl address setup to prog low 48tclcl tghax address hold after prog 48tclcl tdvgl data setup to prog low 48tclcl tghdx data hold after prog 48tclcl tehsh p2.7 (enable) high to vpp 48tclcl tshgl vpp setup to prog low 10 ps tghsl vpp hold after prog 10 ps tglgh prog width 90 110 ps tavqv address to data valid 48tclcl telqv enable low to data valid 48 tclcl tehqz data float after enable o 48tclcl tghgl prog high to prog low 10 ps eprom programming and verification waveforms programming verification ?::=&z ~ .- ~ } address addrfss tavqv data in data out tdvgl tghdx tavgl pu& tghax tshgl d tghsl tglgh tghgl ~wpp t [a/high telqv l tehqz p2.7 272318-18 20
mcs@ 51 controller data sheet revision history datasheets are changed as new device information becomes available. verify with your local intel sales office that you have the latest version before finalizing a design or ordering devices. the following differences exist between this datasheet (272318-002) and the previous version (272318-001): 1. removed qp and qd (commercial with extended burn-in) from table 1. express prefix identification. this datasheet (272318-001) replaces the following datasheets: mcs@ 51 controllers (270048-007) 8051ahp (270279-004) 8751bh (270248-005) 8751 bh express (270708-001) 8752bh (270429-004) 8752bh express (270650-002) 21

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